virtual clock source latency

Just looking at the output side first, what's latching the data being sent, i.e. what is the FPGA driving and how is that external device clocked? If you only look at the time from the software driven register to the output, and let's say that's 5ns, when is that going to be latched by the external device? What delay would make that fail, i.e. would 6ns from the register to the output fail, or 10ns?

One other way to think of the clock tree and the data delay is that they're really part of the same thing(which TimeQuest calls Data Arrival Path). For example, let's say we could move the delays around. For example, let's say the clock path was shortened by 10ns, but the data path out was increased by 10ns. Now, the data will change on the output at the exact same time, but if you're just measuring from the register out, then you will get a very different analysis, but by measuring the clock tree you will get the same result and this juggling of numbers won't affect the slack(as it shouldn't).

(Note that the general problem is over-thinking these things.)