virtual clock source latency

Well, I have the problem on both ends, output setup and input hold. But obviously caused by the same issue.

I can definitely fix that with a multicycle. But is that the best way?

I could as well do something source synchronous (what is not completely wrong), but there is no clock pin resp. no output clock at all.

Then I'm not sure if I understand you correctly: You write if the clock delay doesn't matter, then it is source-synchronous. Isn't that the other way round?

In my case, the clock insertation delay does not matter. Just the timing analysis forces me to respect that from the pin point of view, because this delay is always included in the arrival path.