VHDL writing in memory

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OK for the range.

My hold local variable is there for the signals to keep a value for several clock cycles. Maybe it's not the good way of doing that. Tell me how to do that, I'm not used to it...

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you already done that. Here is my version

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ctrl is
    port(
        data        : out std_logic_vector(7 downto 0);
        wen        : out std_logic := '0';
        addr        : out std_logic_vector(14 downto 0):=(others=>'0');
        clk        : in std_logic);
end ctrl;
architecture rtl of ctrl is
    signal count1 : integer range 0 to 15 := 0;
    signal count2 : integer range 0 to 7 := 0;
     
begin
    
    process(clk)
    begin
        if clk'event and clk='1' then
          wen <= '0';
          if count1 /= 15 then
              count1 <= count1 + 1;
          else
              count1 <= 0;
              if count2 /= 7 then
                 count2 <= count2 + 1;
              else
                 count2 <= 0;
                 wen <= '1';
              end if;
           end if;
        end if;
    end process;
    
    data <= std_logic_vector(to_unsigned(count1, data'length));
    addr <= std_logic_vector(to_unsigned(count2, addr'length));
      
end rtl;