Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

VHDL variables in Quartus v9 simulation

Hi, I'm trying to simulate a design in the Quartus v9 simulator. In the VHDL design there are variables within a process that I'd like to view in the simulation, but in the node finder they don...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

--- Quote Start ---

the quartus simulator only runs a post place and route simulation. Depending on how you used your variables, they may have been converted to intermediate logic.

I suggest using modelsim.

--- Quote End ---

The QuartusII 9.1 internal simulator also supports 'functional' simulation, which is RTL and run after Analysis and Synthesis..

But the suggestion to use ModelSim definitely holds, writing testbenches is a lot more powerful than drawing waveforms.