VHDL Package not detected by Modelsim

This is output of verror 19 :

vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive_ver -L cycloneive -L rtl_work -L work -L Fir_left_ch -voptargs="+acc" tb_audio_ctrl_Top.vhd
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive_ver -L cycloneive -L rtl_work -L work -L Fir_left_ch -voptargs=""+acc"" tb_audio_ctrl_Top.vhd
# Start time: 19:01:11 on Mar 16,2022
# ** Error: (vsim-19) Failed to access library 'tb_audio_ctrl_Top' at "tb_audio_ctrl_Top".
#
# No such file or directory. (errno = ENOENT)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./Audio_FIR_filter_run_msim_rtl_vhdl.do PAUSED at line 76
verror 19
#
# common Message # 19:
# The specified library could not be accessed at the specified location.
#
# Verify that the directories in the path exist and have the proper access
#
# permissions and that the "_info" file (with proper access permissions)
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# exists. This message might be preceded or followed by another message
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# that gives more information about the problem.
#
#
#
# The vlib command creates a ModelSim library. The vmap command creates
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# the map from a logical library name to the physical library (directory).
#
# Use the vmap command without arguments to find out how all the libraries
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# are mapped. In the absence of a mapping, the library is searched for in
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# the current working directory.
#
#
#
# One way this problem can occur is if the mapping for the library in your
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# modelsim.ini file contains an environment variable that is not set
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# in your environment.
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#