VHDL: How to find my library in Quartus?

hmm well instead of starting another thread, i'll try to ask here..

I thought that calling that way would fix the problem but i still get the same error i was trying to evade:

--- Quote Start ---

Error: Port "Reset" does not exist in primitive "tff" of instance "tff0"

--- Quote End ---

it happens on this line:

tff0  : entity work.TFF port map( enable, clk, rst, Qout(0));

of this file:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity TFFcounter16bit is
	
	port ( 	enable, clk, rst : in std_logic;
			Qpin	: out unsigned(15 downto 0)
	);
end TFFcounter16bit;
architecture wowee of TFFcounter16bit is
	
	signal Qout : unsigned(15 downto 0);
begin
	
	tff0  : entity work.TFF port map( enable, clk, rst, Qout(0));
	tff1  : entity work.TFF port map( (enable AND Qout(0)), clk, rst, Qout(1));
	tff2  : entity work.TFF port map( ((enable AND Qout(0)) AND Qout(1) ), clk, rst, Qout(2));		
	tff3  : entity work.TFF port map( (((enable AND Qout(0)) AND Qout(1)) AND Qout(2)  ), clk, rst, Qout(3));
	tff4  : entity work.TFF port map( ((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3) ), clk, rst, Qout(4));
	tff5  : entity work.TFF port map( (((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)), clk, rst, Qout(5));
	tff6  : entity work.TFF port map( ((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)), clk, rst, Qout(6));
	tff7  : entity work.TFF port map( (((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)), clk, rst, Qout(7));
	tff8  : entity work.TFF port map( ((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)), clk, rst, Qout(8));
	tff9  : entity work.TFF port map( (((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)), clk, rst, Qout(9));
	tff10 : entity work.TFF port map( ((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)), clk, rst, Qout(10));
	tff11 : entity work.TFF port map( (((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)), clk, rst, Qout(11));
	tff12 : entity work.TFF port map( ((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)), clk, rst, Qout(12));
	tff13 : entity work.TFF port map( (((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)) AND Qout(12)), clk, rst, Qout(13));
	tff14 : entity work.TFF port map( ((((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)) AND Qout(12)) AND Qout(13)), clk, rst, Qout(14));
	tff15 : entity work.TFF port map( (((((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)) AND Qout(12)) AND Qout(13)) AND Qout(14)), clk, rst, Qout(15));
	
	Qpin <= Qout;
	
end wowee;
 

which is instantiated from this file:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity TFF is
	port( T, Clk, Reset	: in std_logic;
			Q			: out std_logic
	);
end TFF;
architecture behavioral of TFF is
	signal buf : std_logic;
begin
	
	process(T, Clk, Reset)
	begin
	
		if(reset = '1') then
			buf <= '0';
		end if;
	
		if(Clk = '1') then
			if(T = '1')then
				buf <= (NOT buf);
			end if;
		end if;
	
	end process;
	
	Q <= buf;
	
end behavioral;
 

Can someone please help?

Thanks

Malik