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Altera_Forum's avatar
Altera_Forum
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12 years ago

Very basic SignalTap question

Hello, I have inherited an old Cyclone II design which is mainly implemented in schematic. I am staying with the older version of Quartus for now (9.1) since there's a lot of native simulation ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

As a first test just use the NEW_DATA_PS as the acq_clk.

If it's failing timing, try switch what edge of NEW_DATA_PS is used in the acquisition.

There's no requirement that the acq_clk be a real 50% duty cycle clock.

My biggest recommendation is to convert the schematic portions of the design to Verilog or VHDL as soon as you can. The schematics are nice for board designers, but their support is dropping quickly, and your simulation tools choices are very limited.

Pete