MingBai
New Contributor
4 years agoVERILOG_MACRO
Dear,
I haved defined a Verilog macro in the .qsf file.
But the results are far from expectations.
Is it a software bug?
Hi Ming Bai,
It would be helpful if you can kindly explain further in detail about the issue.
If the issue has been resolved, kindly do let me know.
Regards,
Pavee