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Altera_Forum
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11 years ago

Verilog Initial Block Value of 3-bit reg ignored by Quartus 14.0 synthesis

Hi, I am using a Verilog initial block to power-up certain reg's to high. My code looks something like this: reg a; reg[1:0] b; reg[2:0] c; initial begin a = 1'b0; ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

I believe I figured this out. Quartus inferred that 'c' was a state machine having a reset value of 0, so powered up 'c' to 0 without alerting me of having synthesized away the initial assignment from the Verilog code. Quartus optimizations can be dangerous when they change the logic from the HDL code.