Using VHDL to generate 20Mhz sine wave and visualizing with a 10bit DAC

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Oh, now I understand. How about Cordic algorithm?

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First try simple solution. If your required tone is 20MHz and your sampling clock is multiple of 20 e.g. 100MHz then all you need is a cycle of sine data of 100/20 = 5 data points. This can be implemented as basic logic with a counter to read them sequentially.

If your sampling clock divides with fractional result then you need a larger LUT (possibly altera NCO ip). people use cordic to avoid multipliers at the expense of more logic.