Using VHDL to generate 20Mhz sine wave and visualizing with a 10bit DAC

The most simple way is to generate a 20 MHz square wave and extract the fundamental wave by a low-pass filter. Otherwise you need to generate a higher output data rate (e.g. 100 or 200 MS/s) to get a halfway continuous output signal. Data rates of several 100 MS/s aren't a problem for recent FPGA and DAC devices, but I fear you won't find a suitable DAC in DIP package. There are a few devices like ADV7120 (8 Bit, 80 MS/s). You may want to use a SOIC to DIP adapter board however.