Using 2 inputs to Clock MUX doesn't result in correct answer

The real design has lots of clocks, but this was happening on a design where there is the ALTCLKCTRL block and one PLL with all signals coming from the IO; that is it 2 IP blocks and connections. I need these PIN assignments as that is what I have access to on the Development Board; so they are not changing.

Let me package up the example and attach it to this case. It is so trivial it should work but I am baffled why the tool cannot do this. This might take me today to get approval to move this test design out of our secure area. Sorry don't have access to Quartus anywhere else for this project.

Thanks,

TomT...