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ThomasTessier's avatar
ThomasTessier
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Using 2 inputs to Clock MUX doesn't result in correct answer

I have a design were I am trying to use the Input Clock MUX to Switch between two input pin clock ports. The PLLs are in platform designer and I get the following warning: Warning: test_system_qsy...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Spitballing here. Since your two reference clocks are different, you may be running into the issue mentioned here about the second reference clock frequency (though I'm just noticing you mentioned matching the frequencies and running into the same issue): https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/ip-core-parameters-clock-switchover-tab.html

Have you considered using the clock control block instead? https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altclock.pdf

Sorry I was thinking of Pro. It's called System View there instead of System Contents. And you can access the Block Symbol tab from the View menu and then select a component to view all the component interfaces and individual signals.

ThomasTessier's avatar
ThomasTessier
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Here is the block view, Platform Designer believes it will have 2 clocks and the switch controls. But after Fitter, I look at the technology view and that isn't the case. Furthermore the signals extswitch and activeclk are on my QSYS generated interface but are not connected to this PLL like I expected. So Platform Designer is happy but Quartus Fitter is not happy.

Yes I did fudge it so both clocks had the same frequency into the tool and I got the same wrong result?

I do have the clock control block in the design for these two clocks, but I think you are saying I can have both clocks coming into one clock control block. Let me investigate more and get back to you.

TomT...

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Are you saying that extswitch is just optimized away and not connected anywhere outside the system? You have it exported in Platform Designer so you have it connected to other logic or it's connected directly to an I/O pin. Are you saying that it's just gone from the design after compilation?

    • ThomasTessier's avatar
      ThomasTessier
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      So this is the RTL view of the new ALTCLKCTRL block that I have put in. I made sure the two inclk pins only go to this block. clkselect is coming from a programmable register inside our Avalon Design so I know it is functional.

      This is the MAPPED view, notice that the two clocks: clkin_50_bot and hsma_clk_in0 are now disconnected?

      TomT...

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        2 years ago

        Is your design complete and the clocks are connected to and clocking logic? If not, things will get optimized away like this.