Forum Discussion
makotolagano
New Contributor
New ContributorUnconstrained base clock in state machine design
I am trying to make a state machine for controlling LEDs as tail lights are controlled on Ford Thunderbird. The board I'm using is DE0 Nano with Cyclone IV.
The state machine part is working fine, ...
You created clk_50 as a virtual clock instead of a base clock because you didn’t set a target (typically with get_ports). Then you have to create a generated clock with the source as clk_50 and the target as the output of your clock divider and accurately describe the relationship between the two. You also should have input and output delay constraints for the I/O.
makotolaganoNew Contributor
New ContributorI have generated real base clock and generated_clock that goes out of my clock divider and accurately described relationship between the two clocks. Also, I defined constraints for I/O. The design now works perfectly as I wanted it to work. From now on I will pay much more attention to timing analysis.
Thank You so much, this made my day!
sstrell
Super Contributor
Super ContributorAwesome. Glad I could help.
