Forum Discussion
New ContributorUnconstrained base clock in state machine design
You created clk_50 as a virtual clock instead of a base clock because you didn’t set a target (typically with get_ports). Then you have to create a generated clock with the source as clk_50 and the target as the output of your clock divider and accurately describe the relationship between the two. You also should have input and output delay constraints for the I/O.
New ContributorThank You for your answer.
Tried removing clk_reg from sensitivity list in clk_reg_logic process and I'm still facing the same problem. I understand that clk_reg in sensitivity list of that process was not a need, because there's no event happening on clk_reg toggle.
Here's my .sdc file (filte type is not supported for upload, so there is a screenshot) and the screenshot of warnings I get while compiling this design.
Super ContributorYou created clk_50 as a virtual clock instead of a base clock because you didn’t set a target (typically with get_ports). Then you have to create a generated clock with the source as clk_50 and the target as the output of your clock divider and accurately describe the relationship between the two. You also should have input and output delay constraints for the I/O.
