UART and MODELSIM ALTERA (code attached)

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Yes, it is. You have separated out all of your combinatorial logic into one process, and then registered it in another.

Aslong as they are placed in a clocked process that uses the correct clock, then its fine.

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-- register byte_reg syncronized;
process(clk, reset)       begin
      if (reset = '1') then
         state_reg <= idle;
         baud_cnt_reg <= (others => '0');
         bits_cnt_reg <= (others => '0');
         byte_reg <= (others => '0');
      elsif (clk'event and clk='1') then
         state_reg <= state_next;
         baud_cnt_reg <= baud_cnt_next; 
         bits_cnt_reg <= bits_cnt_next; 
         byte_reg <= byte_next;
      end if;
   end process;
...
-- left concatenate the new bit, assuming the bits are sent LSB to MSB
-- other process (FSM).
 byte_next <= rx & byte_reg(7 downto 1);
...
-- out of any process, combinatorial logic.
-- Put the byte read on the output bus.
   dout <= byte_reg;