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just register them directly:
signal rd_r : std_logic_vector(1 downto 0);
signal serial_rx_r : std_logic_vector(1 downto 0);
process(clk)
begin
if rising_edge(clk) then
serial_rx_r <= serial_rx_r(0) & serial_rx;
rd_r <= rd_r(0) & rd;
end if;
end if;
Then use rd_r(1) instead of the origional input "rd" and the same for serial_rx
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Hi tricky, I am doing this already, for example, in the line 110 from the rx_uart.vhd:
-- left concatenate the new bit, assuming the bits are sent LSB to MSB
byte_next <= rx & byte_reg(7 downto 1);
Maybe the problem is with the FIFO megafunction?
I am using the SCFIFO from altera. So, the input "rd" from this SCFIFO is connected with the output "rx_done_tick" from rx_uart.vhd.
Maybe I should use the DCFIFO, which I read that it is better for deal with metastability.
I noted too that the counter from mod_27.vhdl does not flash the leds to indicate that the counter inside is working.
The outputs in this vhdl file are in this way:
-- output logic
q <= std_logic_vector(r_reg);
max_tick <= '1' when r_reg=(M-1) else '0';
I think it should be corrected as you said. I'll try to double register these two outputs and test the counter first.
Then I ll increment the circuitry with uart, then with the FIFO, and see if it works.
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