UART and MODELSIM ALTERA (code attached)

Thank Tricky, I will try it but, as soon as I am modeling the uart through Flip-Flops,

and using two signals to do in this way, I am thinking witch is the best practice to implement it.

As a beginner Is it suggested to do it in the sequential logic process......or in the combinational part, outside the process?

sequential logic process:

entity

...

port( rx: in std_logic );

...

archtecture

...

-- two signals representing the Next State Logic register for a byte comming in port rx.

signal b_reg, b_next: std_logic_vector(7 downto 0);

-- other two signals representing the other register

signal other_b_reg, other_b_next: std_logic_vector(7 downto 0);

...

process(clk, reset)

...

-- next state logic for b and...

b_reg <= b_next;

-- ...the other register.

other_b_next <= b_reg;

other_b_reg <= other_b_next;

combinational logic:

...

process(clk,rst)

...

end process;

...

process(sensitivity list)

....

end process;

...

--outside the process.

b_reg <= b_next;

other_b_next <= b_reg;

other_b_reg <= other_b_next;

or even do i need another case statment in the finite state machine process just to pass the value from one signal to the other?

It seems that we have a hot topic here (Views: >1,218).

Thanks,