Honored Contributor
Honored ContributorSorry, maybe I couldn't understand what you are trying to tell me, but,
I suppose that I am dealing with two clocks, 50MHz (board) and the frequency of the UART (1.8KHz approximate frequency when 115200bps). the uart signal comming from my PC is operating in 115200bps, so 1.8KHz, the RS-232 on the board is, I think, dealing with this signal in 1.8KHz. The RS-232 on the board sends the serial data to the FPGA pin UART_RXD (PIN_D21) in 1.8KHz. The FPGa and all the components in VHDL are working with 50MHz, trhough the pins "clk" in each component. The mod27 component converts the 50MHz clock signal to the ~1.8KHz clock signal including the oversampling of each bit of the data comming: The mod27 does it counting 27 cycles of 50MHz and generating one pulse. The Uart rx count 7 of these pulses and read the start bit from the first byte. The uart rx counts 16 of these pulses and read the rest of bits from the first byte. Why are they not syncronized inside FPGA if the "clk" input from them are conecteted to the 50MHz clock of the board?
