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I mean the serial RX and rd inputs to the system. If they are not synchronised to the 50MHz clock externally then you will have problems sampling them inside ther FPGA. They need to be at least double registered to avoid metastability problems and glitching.
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All the components are connected with the 50MHz clock from the board, as it can be seen in the schematic, through the "clk" inputs of each of the three components.
As I am using the De2-70 ep2c70f896c6 Cyclone II, here (
http://wiki.icmc.usp.br/images/0/04/de2-70-pins.txt)we can see the information about the pins of this board, i am using PIN_AD15 for 50MHz clock associated with the input named "clock_50MHz" in the schematic. This input is linked to the "clk" inputs of the three components.
This "clk" input is the external 50MHz syncronization that the three components are using.
Inside of mod_27_uart.vhd (
http://www.alteraforum.com/forum/attachment.php?attachmentid=8640&d=1395413992) , I count the 27 cicles of 50MHz and generate one pulse to rx_uart.vhd (
http://www.alteraforum.com/forum/attachment.php?attachmentid=8641&d=1395413997). In turn, the rx_uart.vhd (
http://www.alteraforum.com/forum/attachment.php?attachmentid=8641&d=1395413997) counts 16 pulses comming from mod_27_uart.vhd (
http://www.alteraforum.com/forum/attachment.php?attachmentid=8640&d=1395413992) to sample one bit (for start bit it counts just 8 pulses). All of them work with 50MHz.
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