Honored Contributor
Honored ContributorYes, the mod_27_uart.vhd does that.
It takes 27 cicles from 50MHz and generates one pulse to RX. After 16 (oversampling) cicles, the RX consider to sample a byte. It means that the RX does sampling in the middle of each byte that comes in uart. For ease of implementation, the FIFO is a megafunction, so it may ensure that it works well in the project. I atacched a table showing pins association. I folow this calculation to convert 50Mhz to 115200bps: ------------------------------------------------------------------------------------------------------------------------------- 50 mhz (board) to 1.841mhz (uart 115200) In 115200bps, one bit is send in 0,000008681 seconds. If each bit is sampled 16 times, each sample must occur in 0,000000543 seconds. This is equivalent to say: 1841620,626151013 Hertz (1.841,620 MHz ~ 1.841 MHz) So, in one cicle of 50MHz, I need to wait 50MHz/1.841MHz cicles (or 27,1 ciclos) of 50MHz to read each of one 16 samples for each bit. ------------------------------------------------------------------------------------------------------------------------------- In resume, after 27 cicles from 50Mhz, I count one tick. After 16 ticks, I read a byte in TX. (Of course, for the first bit (start bit) I wait just 7 ticks.)
