True DPRAM IP

Hi Dave

Actually I felt confident that a true implementation would be ok.

It's not the first time I use DPRAM but rather more the first time I wanted to include it it a simulation environment.

Initially we started the design on 11.1 SP2, then, for the documentation purposes of the issue I switched to an other computer with 10.1, the issue is strictly the same/

Regarding simulation it isn't always that straightforward as you state. We always prepare for simulation regardless if the timing analysis is good or not. My flow is with RTL Precision from Mentor and the project is a SOC emulation. With the constraints given there, the SDC generation is much more User friendly and the result always ok.

So there is debug and sometimes simulation if something goes wrong for an easier monitoring of the signals. As you know SignalTap is nice but somehow intrusive and you need to re-compile whenever you forgot a signal to monitor, this is not in line with productivity constraints.

To conclude, I suspect an erroneous model. Doing the RTL simulation with the VHO is ok, switching to gate level it goes out of tracks.

Should be easy to correct for ALTERA.

K.r.

Thomas