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implementing this true DPRAM design implemented in FPGA and monitored with a SignalTap works perfectly.
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Great!
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I will now log a service request in MySupport to check out Altera's position on that.
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Before you do, make sure to test the gate level simulation using the latest edition of the Quartus tools. You will not get any support for old tools. Your megawizard instance was generated using 10.1. Try again using 11.1sp1 or 11.1sp2.
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Cause all this is used in a more complex system of coarse and I will need to gate level simulate all this.
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Why? If your functionality is correct with an RTL simulation, and synthesis meetings timing (no errors from TimeQuest), then you do not need a gate level simulation. You really only need that to track down issues with the hardware being inconsistent with the RTL simulation, i.e., a SignalTap II trace that is inconsistent with the RTL trace. I very rarely need to use a gate level simulation (its too slow, and why bother when the hardware is right next to me).
Cheers,
Dave
Honored Contributor
