True DPRAM IP

Dear all

As all of us could have guessed, implementing this true DPRAM design implemented in FPGA and monitored with a SignalTap works perfectly.

You can check the screen shot here attached, all ok.

A state machine performs

1. Read cycle to an address

2. Write cycle to the same address with new data

3. Read back of the new data

For an easier reading only lower sections of address and data buses are shown.

With an appropriate SignalTap clock rate one can almost get information on access time.

Thanks for having accompanied me till here.

I will now log a service request in MySupport to check out Altera's position on that.

Cause all this is used in a more complex system of coarse and I will need to gate level simulate all this.

Bye and looking forwards to talking to you soon.

Thomas