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Altera_Forum's avatar
Altera_Forum
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13 years ago

True DPRAM IP

Hi I need a true dual port RAM with 2 read and write accesses for a Stratix 4 device; With the MegaWizard this is in fact very easy but while trying to simulate with ModelSim I see a few issues:...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Dear all

Thanks for your kind help and advices.

I decided to give a quick try with a specific embedded test design and a SignalTap.

I believe that this will give a clear idea and that there's clearly a possible gatelevel registering of the WREN.

I will let you know with consistent data asap.

Nice day to all of you!

K.r.

Thomas