Hi Thomas,
Here's a testbench that you can use as a reference to test the gate level simulation.
Altera altsyncram dual-port RAM testbench
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5/2/2012 D. W. Hawkins (dwh@ovro.caltech.edu)
1. Start Modelsim
2. Change directory to the source folder
3. Type 'source sim.tcl' in the Modelsim console
4. The wave window will show the waveforms, and the console
will output the following messages:
# ==============================================================================# Altera dual-port RAM testbench# ==============================================================================# # ------------------------------------------------------------------------------# Test# 1: Fill the RAM# ------------------------------------------------------------------------------# 1000 ns: Fill 128 locations of the RAM with a count pattern using port A# # ------------------------------------------------------------------------------# Test# 2: Check the RAM using port A# ------------------------------------------------------------------------------# 3028 ns: Check 128 locations of the RAM match the expected count pattern# 4076 ns: All checks passed ok!# # ------------------------------------------------------------------------------# Test# 3: Check the RAM using port B# ------------------------------------------------------------------------------# 5076 ns: Check 128 locations of the RAM match the expected count pattern# 7690 ns: All checks passed ok!# # ------------------------------------------------------------------------------# Simulation Completed!# ------------------------------------------------------------------------------
Perhaps this will help in determining the source of your problem.
Cheers,
Dave