True DPRAM IP

Hi Thomas,

--- Quote Start ---

I need a true dual port RAM with 2 read and write accesses for a Stratix 4 device;

With the MegaWizard this is in fact very easy but while trying to simulate with ModelSim I see a few issues:

1) Write cycles:

While writing several cycles in a row, on the 'A' side, the cycle which follows (which WREN = '0') still causes the simulation environment to write erroneous data.

It actually writes the data which is on the D_IN bus.

This is confirmed by reading it from the other side (the 'B' side) the data is there.

Does anybody have an idea?

2)Number of clock cycles:

It seems that at least 2 cycles are required for a read operation (or 1 if there's a pipeline behind in case of continuous operation) and 1 cycle for write operation is enough.

Is there a consistent documentation for this case with timing diagrams, I have the Internal ROM RAM User Guide but there is nothing clear there.

--- Quote End ---

I've used dual-port RAM on Stratix IV devices. I've never seen problems.

I suspect your write-enable timing is probably the source of your problem.

If you could post a simple testbench, with just an altsyncram component and your test sequence, then I'll take a look at the code.

Cheers,

Dave