tricky problems

Generally, syntactical correct VHDL code must not necessarily involve correct logic operation in FPGA implementation. Before you adopt code examples from a book, consider that they may be intended for simulation purposes only.

--- Quote Start ---

But normaly

process(clk)

if(clk='1')

and

process(clk)

if(clk'event and clk='1')

should be equivalent.

--- Quote End ---

not at all!

If you are interested to produce working FPGA code rather than trying out, which code examples from literature won't work in synthesized VHDL (I guess, you are), then you should start with the Quartus VHDL design templates for counters and state machines. Or consult a text book dedicated to synthesizable VHDL for FPGA.