New ContributorHello.
I'm triyng to do a Gate Level Simulation of a simple Latch D design and I want to use the Timing model slow 85C but that option didn't appears.
It there any way to add it?
I´m using Quartus 18.1 and a Cyclone lV E
Super ContributorHi Oscar.
Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is supported only for the Arria II GX/GZ, Cyclone IV, MAX II, MAX V, and Stratix IV device families. Use Timing Analyzer static timing analysis rather than gate-level timing simulation.
Super ContributorOscar,
May I know if there is any update?
New ContributorHello
Thank you four your answer, as you say Gate-level simulation is slow but it was part of a practice, and my problem was that I selected the wrong device family.
