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Altera_Forum's avatar
Altera_Forum
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11 years ago

Timing issue

Hi , i compile my project with Quartus and i have critical error : "Timing requierements not met" and the TimeQuest Timing Analyzer painted red . The clk_in Frequency to the FPGA is 25MHz en...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Why do you have 1.5ns of clock skew? Is this from an incoming I/O port, or something within the device? (I/O always have clock skew, while internally you can often get around it). Basically, is this a real path that needs to be analyzed and meet timing, and does it make sense to have 1.5ns of skew?

If it's an I/O path, can you increase the delay chain in the I/O? Maybe assign the input register to a location further from the I/O? (It's really hard to say without more information, so just some quick ideas.)