Timing failure: different clock delay for launch and latch clock

Hi Rysc

I can see CLKCTRL_G6 and CLKCTRL_G4 under the location column in my clock path. After running report_timing with -show_routing I can also see some GCLK_CLUSTER*. The clock path for both Data arrival and Data Required is same up to the very last SPINE_CLK* location.

Can you explain the term Clock Pessimism? I understand that when calculating setup time we take the max delays to account for the worst case. And Clock Uncertainty is a kind of a margin within which the clock can arrive.

I see at the bottom of Data Required Path 'clock pessimism removed' which is about 700ps? What is the tool doing here?

A point to note is that we are using a hard IP for a serial interface. We use the clock generated by that IP as our application clock. The reason for this was that we wanted to avoid any clock crossing between the interface and our application. I am not sure if this is the right practice but this is making our clock path really long.

Is it worth trying to generate a same clock in the application using a new pll? Is it safe and will the 2 clocks match exactly?

Please see the attached report_timing output with routing(sorry *.xlsx file was not supported).

Thanks