Timing Constraints for Serial Interface

I was reading in the classic timing analyzer handbook about the maximum and minimum delay assignment.

I tired to place an assignment from the register output to the FPGA pin, but the actual bit in the register cannot be found. Perhaps it got synthesized away.

My code is as follows:

Trx_Request_Reg := Trx_Request_Reg(46 downto 0) & '0';

TRX_TX <= Trx_Request_Reg(47);

where TRX_TX is the output pin of the FPGA and Trx_Request_Reg holds the bits to be transmitted.

On each clock edge I shift the bit once to the left and clock out bit 47. When I go to the node finder in the assignment editor, to place FROM TRX_Request_Reg(47) TO TRX_TX, I see every bit in the Trx_Request_Reg excpet for bit 47. I placed the filter as "Post Synthesis" in the node finder. These are the types of things that really confuse me. The handbook makes it seem like it simple, and it probably is, but its my experience at doing this that lets me down.

Also some bits appear twice in the node finder, for example TRX_Request_Reg(6) and TRX_Request_Reg(6)~2179. Why do some appear twice and with a ~2179 or other number?

Thanks for any further advice.