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I have to implement a serial interface to send and rx data to/from another board...
Basically, I have 3 LVDS lines, a chip select, a data line and a clock (83MHz). on the tranmitter side and a receiving line which receives the data from the other board (another FPGA) a specified number of cycles after chip selct falls. What I was concerned about was one of the signals, for example the clock getting delayed a fraction more than the data and at the receieving end the incorrect data being read. From scope shots i can see a small delay in the clock signal arriving between both boards (maybe 1ns I would guess, through a 5 inch long cable).
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If you are using the hard-silicon SERDES, then the timing should be fine as long as the RSKM (receiver skew margin) on the receiving device is OK. The RSKM will be affected by the relative board etch delays of the signals with respect to each other (which you mentioned), not the total board delay.
If you are not using the hard-silicon SERDES, then your transmitting interface needs to be constrained as a source-synchronous interface. The data output timing should be constrained with respect to the clock output timing. (This is not the same thing as tco. As I said in my previous post, tco is referenced to the FPGA input clock device pin.) TimeQuest is the preferred Timing Analyzer for constraining source-synchronous interfaces.
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