Timing constraints for output ports

Thanks rbugalho for replying. After creating P4_clk at the output pin, the rest still the same with regard to the set_output_delay min/max command? My guess is yes, but I could be wrong.Anyway, I'll try your suggestion on Monday. Have a nice weekend guys

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You apply the same concept: you create a derived clock at the output pin.However, you need 2 steps.First, create the 2.048 MHz clock at the output of the FSMcreate_generated_clock -source $pllClock -divide_by 2 -name "clk_2048" [get_registers fsm_clock_output]Then, you create the P4_clock output from thatcreate_generated_clock -source clk_2048 -name "P4_clock" [get_ports P4]Virtual clocks are clocks which do not exist inside the FPGA.This clock exists, as it's generated inside the FPGA, even if does not drive any logic inside the FPGA.And in this case, it better represents your system than P4_ext.The "P4_ext" virtual clock you described has zero delay, in regard to the P2_clk.While the "P4_clock" does include all the delays inside the FPGA, from the P2_Clk pin to the PLL to the FSM to the P4 output pin.

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