Timing constraints for output ports

Why I don't need P4_ext now? The virtual clock is mentioned everywheret in IO constrain. P4 is not directly drives by PLL. PLL divides the incoming clock (@32.768MHz) by 8 to get 4.096MH and the FSM runs on this 4.096MHz to generate 2.048MHZ. The reason why there's this small difference is because the truncation of the compiler.

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PS: You don't need it now, but when you created the P4_ext clock, you probably gave it the wrong period.You have a 30.518 ns P2 clock, which you then derive with a PLL to obtain P4. I assume you get P4 by dividing P1 by 16. This means P4 will have a period of 30.518 * 16 => 488.288 ns (which is actually 2.04797169 MHz).Instead, you said P4_ext has a period of 488.281. This is a tiny difference, but it might cause problems with the tools.

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