Timing constraints for output ports

P4 is actually drived from the output of the PLL. The FSM is running on the output clock of the PLL at 4.096MHz. The FSM drives P4 at 2.048 MHz. This relationship is useful to decoding CMI because it helps to sample the data stream twice during one bit interval. Therefore I have the launch clock running at 4.096MHz (because data is launched from the FSM). The latch clock is running at half the rate (2.048MHz). So how should I treat this 2.048MHz clock on P4 port? I believe it's a virtual clock as it doesn't interact with anything else inside the FPGA, but I am not sure how to constrain it?

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Since the FPGA provides the clock to the HDB3 encoder, it's best to start by creating a clock on the FPGA's clock output pin.I assume P4 is the output of inst5|altpll_component|auto_generated|pll1|clk[0]create_clock -source inst5|altpll_component|auto_generated|pll1|clk[0] -name P4_clock [get_ports P4]You can then specify your output delay constrains in regard to this P4_clock. If your external device is sampling on the falling edge, then you should use -clock_fall P4_clock, instead of -clock P4_clock.If your device has a 40 ns tSu and a 40 ns Th, then you should specify that in the delays.set_output_delay -clock_fall P4_clock -max 40 [get_ports P5]set_output_delay -clock_fall P4_clock -min -40 [get_ports P5]

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