Timing constraints for output ports

PS: You don't need it now, but when you created the P4_ext clock, you probably gave it the wrong period.

You have a 30.518 ns P2 clock, which you then derive with a PLL to obtain P4.

I assume you get P4 by dividing P1 by 16. This means P4 will have a period of 30.518 * 16 => 488.288 ns (which is actually 2.04797169 MHz).

Instead, you said P4_ext has a period of 488.281. This is a tiny difference, but it might cause problems with the tools.