Timing constraints for output ports

Since the FPGA provides the clock to the HDB3 encoder, it's best to start by creating a clock on the FPGA's clock output pin.

I assume P4 is the output of inst5|altpll_component|auto_generated|pll1|clk[0]

create_clock -source inst5|altpll_component|auto_generated|pll1|clk[0] -name P4_clock [get_ports P4]

You can then specify your output delay constrains in regard to this P4_clock.

If your external device is sampling on the falling edge, then you should use -clock_fall P4_clock, instead of -clock P4_clock.

If your device has a 40 ns tSu and a 40 ns Th, then you should specify that in the delays.

set_output_delay -clock_fall P4_clock -max 40 [get_ports P5]

set_output_delay -clock_fall P4_clock -min -40 [get_ports P5]