Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Timing Closure with a Gated Clock

I'm making a design that processes data in several stages. In the first stage data is clocked in at 60MHz, but is only present some of the time. Once 50 samples are received a resulting value is pass...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Oh yeah, using a ALTCLKCTRL block is also ok.

In any case, if you go with a gated clock, I'd use the same kind of multi-cycle exceptions as with clock enable.

If you fiddle enough with get_fanouts, you might be able to find to automatically constrain every affected path.

OTOH, I'm not sure if this is correct but here's an idea to constrain the gated clock:

create_generated_clock -source clk60M -divide_by 50 -edges {0 8.333333}