Timing Closure with a Gated Clock

When I mentioned using an enable I wasn't referring to gating the clock with combinational logic. Altera provides an ALTCLKCTRL megafunction that allows you to enable and disable a clock without skew. The advantage of this to a PLL is that I wouldn't have to worry about buffering all the signals that need to cross the clock boundary since it would still launch at the right time. It seems like this would be the most hardware efficient way to achieve what I'm trying, but I haven't used this feature before. Seems like the best solution might be to use the clock controller along with setting the multicycle timing paths. It would be nice if there was a way to declare that the output of the clock controller was slower though so I didn't have to flag every downstream net.