Timing Closure with a Gated Clock

Honored Contributor

13 years ago

Logic generated clocks (gating, clock dividers) are best avoided in FPGAs because those clocks tend to have large skews.

It's not forbidden, but timing closure can get difficult.

Use PLLs to generate other clocks or use clock enables if you can't/don't want to use a PLL.

Use clock enable instead of clock gating.

So, two options for you.

a) generate a slower clock (1.2 MHz for example?) using a PLL and use that to drive your slow logic.

Just add the derive_pll_clocks and derive_clock_uncertainty commands to your SDC.

b) run everything in the 60 MHz clock and use a clock enable and add multi-cycle exceptions to relax the constraints.

So, if I have an enable condition that's common to regAA and regBB and is only active one in every 50 cycles, I can use

set_multicycle_path -setup 50 -from [get_registers regAA] -to [get_registers regBB]

set_multicycle_path -hold 49 -from [get_registers regAA] -to [get_registers regBB]

You can also automate it a bit

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