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Altera_Forum
Honored Contributor
11 years agoAs a late follow-up. I played around with embedding SDC statements in HDL and found two solutions.
1. A simplified variant, assigning all toggle inputs to a single clock constraintattribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is
"-name SDC_STATEMENT ""set_false_path -from "";" &
"-name SDC_STATEMENT ""create_clock -period 10 ] -name ce_sync"""; 2. Embedding the complete SDC loop construct enumerating the clocks in a single SDC_STATEMENT line attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is
"-name SDC_STATEMENT ""set_false_path -from "";" &
"-name SDC_STATEMENT ""set regs ;" &
"set n 0;foreach_in_collection reg $regs {;" &
"set clk ];" &
"create_clock -period 10 -name ce_sync_input${n} ;" &
"set_clock_groups -exclusive -group ;incr n;}"""; Illustrating somehow Rysc's comment about the clunky way of embedding Timequest statements, but working though. A possible drawback of embedded clock constraints, they are executed before the regular SDC files and may block other create_clock statements to a node. Best wishes, Frank