Forum Discussion
Altera_Forum
Honored Contributor
13 years agoI've figured out one method that defines the signals on each synchronizer clock input as a clock that is then placed in its own asynchronous clock group;
# sync_pulse.sdc
# Find all the synchronizers in the design
set regs
# For each synchronizer find the name of the signal driving# the clock input port, and create a named clock constraint.# Name the synchronizer inputs sync_pulse_input${n}, where# n = 0, 1, 2, etc, so the synchronizer input names can be filtered# from #
set n 0
foreach_in_collection reg $regs {
set clk ]
create_clock -period 1000 -name sync_pulse_input${n}
set_clock_groups -exclusive -group
incr n
}
TimeQuest now identifies the signals as clocks, and I named them such that if I wanted to do something with the real clocks in the design, I could easily distinguish between the real clocks and sync_pulse inputs. Eg., this design has two real clocks, the JTAG and 50MHz input clocks, and three synchronizers
tcl> set clks
_col17
tcl> query_collection -report -all $clks
altera_reserved_tck
clkin_50MHz
sync_pulse_input0
sync_pulse_input1
sync_pulse_input2
This achieves the goal of informing TimeQuest that each synchronizer input is a clock-like signal that can be ignored. Am I abusing TimeQuest using this particular method? Cheers, Dave