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I own TimeQuest maintenance and development now, although I did not design TimeQuest.
rbugalho is generally right in this thread. The Th, Tco, Tsu params are refecting real circuit delays, more precisely, relative delays between two ports on the register circuitry.
The documentation clearly states how these params are used in the equations. And the values can be positive or negative, depending on the HW design.
My team is SW and do not modify the model delay values from the ICDesign teams without very good reasons; and we have no good reasons to make these params positive.
Of course, model bugs appear all the time, so we appreciate the users reporting perceived problems. But the micro params on these registers, since they are so visible, have been scrutinized heavily by the SW and HW modeling teams (for mature FPGA products) and should be correct by now.
Chris Wysocki
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Thanks Chris for your reply but unfortunately you are avoiding direst answer.
I understand Tsu/Th can be negative if relative delays exist at data/clock ports.
But then you are implying that the uTsu/uTh definition includes these delays and so can be either positive or negative.
No problem but why not then report uTsu/uTh as they are.
Take this post specifically. We have this set of data:
data required path:
total incr rf type fan out location element
20.000 0.000 source latency
20.000 0.000 1 pin_31 clk clk
20.000 0.000 rr ic 1 ioibuf_x0_y14_n1 clk~input|i
20.990 0.990 rr cell 1 ioibuf_x0_y14_n1 clk~input|o
21.182 0.192 rr ic 1 clkctrl_g4 clk~inputclkctrl|inclk[0]
21.182 0.000 rr cell 2 clkctrl_g4 clk~inputclkctrl|outclk
22.339 1.157 rr ic 1 ff_x1_y10_n17 q~reg0|clk
22.957 0.618 rr cell 1 ff_x1_y10_n17 q~reg0
22.982 0.025 clock pessimism
23.003 0.021 utsu 1 ff_x1_y10_n17 q~reg0
Is uTsu reported positiveor negative?
answer 1: it is positive as implied from final sum then the data required time equation is wrong
answer 2: it is negative so equation is right but report is wrong.
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