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More basic, why can't you have the PLL create multiple clock outputs? I think that would be the easiest solution as they would all be aligned nicely. (I'm a bit surprised the clock enables are that much worse. If you used enables, you would have one global clock line toggling at 320MHz and then a lot of logic that gets enabled/disabled. With this new implementation, you still have the global toggling at 320MHz, but the 160MHz and 80MHz(and probably all of them) are feeding additional Global clock lines, which consumes a decent amount of power.
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I have quite a few choices for user selectable divisors, so I don't have enough PLL outputs or I would have done that. :( However, I will go back and take a look at clock enables again. It's possible that something has changed now that I have more of the system in place. I guess I should be concerned that I have done something that doesn't have an immediately obvious solution.
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