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Altera_Forum's avatar
Altera_Forum
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11 years ago

The simplest "hello" that works with Quartus and ModelSim

I wanted to make a step-by step tutorial, which really works with Quartus and ModelSim.

By trial-and-error method, I came to the result, of making the files Hello_tb.v

module Hello_tb;    reg clock,reset;
    initial
        begin
            $display("Hello world!");
            $finish;
        end
        
        Hello dummy(clock, reset);
endmodule

and Hello.v

module Hello(input clk, input rst);endmodule

My questions are:

1./ Is this the possible minimum for the Hello, which works for Quartus+ModelSim combination?

2./ The "$finish" produced warning "ignoring unsupported system task in the "Analyzis and Elaboration" phase ;

and a note "Note $finish" in ModelSim simulation. So, obviously it is not ignored. What is really the case here?

(I mean: what is ignored and what is not? And, why this misleading message? And, why a standard task is said to be

not supported?)

3./ During simulation, when "$finish" is reached, in a popup window I am asked if I really want to finish.

If I say yes, the simulator window closes.

As I just want to see the result in the "Transcript" window, I say "No" and I can browse the messages in the window,

but also the simulation continues. Is it the intended behaviour?

Thanks for your opinion in advance.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Its not quite the minimum. YOu could remove hello.v altogether.

    I dont know what dummy is. It clearly does nothing.

    Im not sure you really understand what quartus does. It takes your HDL, and converts this code into gates and registers. System calls like $display and $finish are for simulation only, and hence, as you saw, quartus ignores the. With dummy as it is, it means your file will compile in qurtus into absolutly nothing, as it contains no register or gate descriptions.

    So, in answer to 3, yes this is the intended behaviour in simulation. And it is the intended behaviour for synthesis also (ie. generate nothing).