Contributor
Super ContributorLoan I/O means that the pins would not be used for SPI from the HPS anymore. They would be available in the Quartus Pin Planner for you to connect signals from the FPGA side of the device.
It looks like choosing FPGA gives you these connections to the SPI controller: https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/fpga-routing-61665.html
ContributorHi,
Thank you for your answer and wiling to help.
Do you know if I can control these four pins (MISO,MOSI,SCK_SCL and CSn) through FPGA ?
Another question is, when I set the pins as LoanIO, and use the inout wire to link to them in top design file, I got the following error:
Error (169026): Pin hps_gpio_loan57 with I/O standard assignment 2.5 V is incompatible with I/O bank 7A. I/O standard 2.5 V, has a VCCIO requirement of 2.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
The default setting of these loan IO is 2.5 V BTW.
Reguards.
Super ContributorAs the error says, you have other pins in the I/O bank that are set to 3.3 V instead of 2.5V. You either need to change their voltage or move them to different locations in a different I/O bank.
