the clock network delay is different between Timequest report and chip planner

Do not use the Chip Planner for any sort of static timing analysis. TimeQuest is 100% the way to go. Note that every timing analysis has micro-parameters(uTsu, uTh) on the same registers, so timing changes depending on what type of analysis you're doing. Also note that TQ models On-Chip Variation(OCV), so at the same timing model the same path may have two different results, one for setup analysis and one for hold analysis, where the Chip Planner does not do this(and I'd guess always show the slower). Note that the Chip Planner may not show the entire delay, i.e. if going to an output pad, it may not show the final output buffer.

Always use TimeQuest for your true numbers. If you need more detail, change report_timing -detail to full_path. If you want even more than that, add "-show_routing" to the command(although this tends to be too much).

I use Chip Planner all the time with TimeQuest, where TQ gives me the exact numbers, and Chip Planner gives me a nice better visualization of what's going on, but as I've said, the real numebers should be form TQ.