Systemverilog task inside class

Hi~

I wrote a small program, use class.

Inside the class, there is a task help me to do print and add 1 after 1 clk.

However, program isn't run as I want, program will hold @(posedge clk) inside task.

Could someone tell me what's going on??

TINGMING

timescale 1ns/1ps;
class sv_function;
    local int i;
    
    function new();
        i = 0;
    endfunction
    function void print();
        $display("Current i = %d",i);
    endfunction
    
    function void add_1();
        i++;
    endfunction
    
    task op_print(input logic clk);
        print();
        @(posedge clk);
        add_1();
    endtask
endclass
module tb2();
    parameter    CLK_SPEED = 1;
    logic                                 clk;
    logic                                reset;
    
    event                                 EVENT_FINISH_RESET;
    event                                 EVENT_FINISH_STIMULATE;
    
    sv_function                            c = new;
    
    
//-----------------------------------------------------------------------//
//    assignment area
    
//-----------------------------------------------------------------------//
//    Design under test
//-----------------------------------------------------------------------//    
    always
        begin
        clk = 1'b0;
       # CLK_SPEED;
        clk = 1'b1;
       # CLK_SPEED;
        end
//-----------------------------------------------------------------------//
    initial
        begin
        reset = 1'b0;
       # CLK_SPEED;
        reset = 1'b1;
       # (CLK_SPEED*4);
        reset = 1'b0;
        -> EVENT_FINISH_RESET;
        wait(EVENT_FINISH_STIMULATE);
        $display("!!!!!SIMULATION FINISH!!!!!");
       # 100000 $stop;
        end
//-----------------------------------------------------------------------//
//    testbench operation
    initial
        begin        
        wait(EVENT_FINISH_RESET);
        
        c.op_print(clk);
        c.op_print(clk);
        c.op_print(clk);
        
        ->EVENT_FINISH_STIMULATE;
        end
//-----------------------------------------------------------------------//
        
endmodule