SystemVerilog compile error when casting

I am having a problem with Quartus II when trying to cast something in a SystemVerilog file. I have double checked that the file is being compiled as SystemVerilog. My Quartus II version is 9.0.

Here is my enum (I removed some of the entries for the sake of a shorter post.)

package opcode;
    typedef enum logic
    {
        LD = 6'd1,
        ST,
        AND,
        OR
    } opcode;
endpackage: opcode

In the module I have these port declarations:

input instruction_word ins_data,
output opcode::opcode instruction

When I try to do:

assign instruction = ins_data;

I get this error message:

--- Quote Start ---

Error (10928): SystemVerilog error at instruction_demux.sv(14): packed array type cannot be assigned to enum type - enum target requires cast

--- Quote End ---

But when I try to do a cast like so:

assign instruction = opcode::opcode'(ins_data);

I get this error message:

--- Quote Start ---

Error (10170): Verilog HDL syntax error at instruction_demux.sv(14) near text "'"; expecting ";", or ","

--- Quote End ---

I have a book on SystemVerilog which confirms I am supposedly casting correctly. Some Google searches have also indicated as such.

So what am I missing? I have tried wrapping the data type in parenthesis in case the double colon was messing it up and that didn't help either.